1. Technology Field
The present application is related to a particularly compact structure comprising a plurality of vertical channel DRAM cells, with each cell having a self-aligned buried bit line, and to a method of fabricating this compact structure. The present application was filed simultaneously with a related application which relates to fabrication of a gate-all-around word line for a vertical channel DRAM. The related application number is 61/689,238, filed on May 31, 2012 and is entitled: “Method Of Fabricating A Gate-All-Around Word Line For A Vertical Channel Dram”. This related application is hereby incorporated by reference in its entirety.
2. Description of the Background
This section describes background subject matter related to the disclosed embodiments of the present invention. There is no intention, either express or implied, that the background art discussed in this section legally constitutes prior art.
Technology for producing DRAM structures having a 30 nm to 40 nm half pitch has recently been described in the semiconductor processing industry. As part of the constant desire for shrinking the size of device structures, we have been developing vertical channel DRAM structures including trench feature sizes in the range of 5 nm to 10 nm. However, to achieve this goal, it is necessary to develop a different overall device design and a new process for manufacturing the device, both from a point of fabrication feasibility and with an eye on performance stability and reliability.
DRAM devices of a kind currently known in the industry are typically part of an integrated circuit structure and include a bit line and a word line which extends orthogonally relative to the bit line, with the bit line being electrically isolated from the word line. The present invention makes use of these features, but in a unique overall structure comprising a plurality of vertical channel DRAM cells which allows for a smaller feature size and more compact individually-addressable DRAM cells.